An IRIG-B code time system based on FPGA is designed in this paper. FPGA is selected as the master controller, B-format code module is triggered by precious time information, and DC code modulation is finished. Time information is demodulated by revising error design on the basic of DC code. Whole digit design is used by VHDL, all function modules provide by hard logic, so that the rising edge of B-format code is accurate and each rising edge can be used as reference point. The design has been verified and tested through simulation and oscilloscope, the practical application proves that the expected goals are achieved perfectly and the timing is precious and dependable.