本文介绍了利用硬件语言 Veriolg HDL 实现任意分频，特别是小数分频的设计方法， 并在 Quartus II 编程环境下，进行了仿真和调试。
Abstract:
The design method of frequency divider especially the decimal fraction frequency divider based on the VHDL is introduced in this paper. The simulation and testing is finished on QuartusⅡ environment.
