In this paper, FPGA design and implement on code rate configurable Turbo Decoder are introduced. Configurable Turbo decoder supports three code rates: 1/3, 1/6, 1/10 flexibly which decreases the resource consume. Turbo decoder supports fixed iterative times and dynamic iterative times. Code rate configurable Turbo decoder has been implemented on the FPGA chip XC7K325T-2FFG900I of Xilinx Company.