For the quasi-cycli low-density parity-check (LDPC) code, this paper proposes a double modified Min-Sum LDPC decoding algorithm. According the algorithm, QC-LDPC decoder is designed based on FPGA, which effectively reduces the hardware consumption rate and processing delay. Finally, the decoding performance, resource consumption and processing delay of this decoder are analyzed in this paper. On the condition that the complexity of algorithm and the difficulty of implementation do not increase, the information losses in iterative decoding can be effectively reduced and the decoding performance can be improved.