Low-Density Parity-Check Code (LDPC) is widely used in communication system for its near-Shannon limit performance. To satisfy the demand of communication in time variant channel or channel with interference, a multi-rate LDPC with fix code length is designed in this paper. Coding is based on a check matrix with approximate lower triangular structure directly, and multi-rate is achieved by decreasing information bits or increasing check bits. Decoding employs NMSA based on BP algorithm and partially-parallel architecture, thus decoding efficiency and FPGA source consume are both taken into consideration. Finally, a fix code length of 12960 bits LDPC with multi-rate of 2/3, 1/3 and 1/6 is implemented in FPGA.