Low-density parity-check (LDPC) codes as one of the best performance of the error control codes, has been widely used in wireless communication, satellite communication, wireless network and many other digital communication areas. With the development of 5th generation of Tele-communication, the demand for transmission rate in communication system is increasing gradually. A method of parallel LDPC decoder and FPGA implementation are derived in this article, with theoretical analysis and simulation. The method of FPGA Implementation of parallel LDPC serially concatenated systems under different encoding algorithms are realized, and the most appropriate are chosen.