Aiming at the phenomenon of concentrated error code caused by burst channel in communication process, and considering the timeliness of encode, a LDPC code hardware encoder with length of 576 and bit rate of 1/2 in IEEE 802.16e standard is designed, which is described by Verilog, adopts parallel structure design and element prestorage to reduce the resource consumption, and increased working rate, the efficiency of the scheme is verified by simulation and synthesis and implementation results.