The digital down converter with normal structure is not able to meet processing of high-speed sampling signal. A low-complexity structure for digital down converter with flexible degree of parallelism is proposed. Meanwhile, an example is provided which degree of parallelism is 16 and the consumption of hardware resource is analyzed. Simulation results show that the function of proposed digital down converter is correct and consumption of hardware resource is acceptable. Hence, the proposed structure for digital down converter is satisfied with processing of high-speed sampling signal.